The present invention relates to an electrically programmable memory cell and to a method for programming and a method for reading from such a memory cell.
Memory cells of this type, which are also referred to as EEPROM memory cells (EEPROM=Electrically Erasable Programmable Read Only Memory), are sufficiently known.
The basic function of such an EEPROM memory cell is described for example in “Everything a System Engineer Needs to Know About Serial EEPROM Endurance”, AN537, Microchip Technology Inc., 1992, pages 8–15 and 8–16.
FIG. 1 illustrates the fundamental construction of such a memory cell, with a memory transistor Ts′ and a selection transistor Ta′, at the semiconductor level (FIG. 1a) and in the equivalent circuit diagram (FIG. 1b). The basic principle of such a memory cell is based on the alteration of the threshold voltage of the memory transistor Ts′ by electrical charge being stored on a storage electrode 41′ of the memory transistor, said storage electrode being arranged in floating fashion. Depending on the memory state/programming state, when a read voltage is applied to a control electrode 44′, a conducting channel forms in a channel zone of the memory transistor between a drain zone 30′ and a source zone 20′. Said memory state can be read out by applying a voltage between the drain zone 30′ and the source zone 20′ and detecting the presence of a current flow between these connections.
In order to be able to read out the memory state of just one specific memory cell in a memory matrix having a multiplicity of identical memory cells, each memory cell has a selection transistor Ta′. The drain-source path of each memory cell is connected in series with the drain-source path of the memory transistor Ts′, and the gate electrode Ga′ of which is usually connected to a word line of the memory matrix, as will be explained below. At the semiconductor level, the drain zone of the memory transistor and the source zone of the selection transistor are usually formed jointly by the semiconductor zone 30′, which is arranged at a distance from the source zone 20′ of the memory transistor Ts′ and at a distance from the drain zone 60′ of the selection transistor Ta′. These drain and source zones 20′, 30′, 60′ are arranged jointly in a complementarily doped semiconductor layer 10′, which forms the body zone of the memory transistor Ts′ and of the selection transistor Ta′.
The programming of the memory transistor Ts′ is based on the tunnel effect. For this purpose, the insulation layer between the storage electrode 41′ and the semiconductor layer is formed in sections as tunnel insulation layer 45′, which, upon application of a sufficiently large voltage, enables a “tunneling” of charge carriers from the semiconductor body to the storage electrode 41′. In the case of the component in accordance with FIG. 1, said tunnel insulation layer 45′ is formed between the drain zone 30′ and that section of the storage electrode 41′, which lies above said drain zone 30′. This memory cell is programmed by application of a positive programming voltage between the drain zone 30′ and the control electrode Gs′ of the memory transistor. Customary programming voltages are in the region of 20 V. When such a programming voltage is applied, electrons tunnel from the drain zone 30′ to the storage electrode 41′. The storage electrode 41′ is thereby charged negatively, as a result of which the threshold voltage of the memory transistor shifts toward higher values. In order to “erase” the memory cell, the programming voltage with an opposite sign is applied between drain 30′ and control gate Gs′ in order to discharge the storage electrode 41′. In order to read from the memory cell, a read voltage is applied between the control gate Gs′ and the source connection Ss′, said read voltage being chosen such that the memory transistor turns off in the programmed state when the read voltage is present and turns on in the erased state when the read voltage is present.
In the case of the memory cell explained, the selection transistor Ta′ is required in order to apply the programming voltage required for programming the memory cell to the drain zone 30′ of the memory transistor Ts′ during the programming operation. Said programming voltage cannot be applied directly between drain 30′ and gate Gs′ of the memory transistor Ts′, but rather is applied between the drain connection 60′, Da′ of the selection transistor Ta′ and the gate Gs′, 44′ of the memory transistor Ts′, the selection transistor Ta′ being turned on by application of a drive voltage corresponding approximately to the programming voltage. Driving of the selection transistor Ta′ with a drive voltage of the order of magnitude of the programming voltage ensures that the selection transistor Ta′ is turned on throughout the programming operation.
The construction of a memory matrix has a plurality of such memory cells is explained below with reference to FIG. 2. FIG. 2 illustrates a memory matrix having only four memory cells Z11′, Z12′, Z21′, Z22′, of which two are in each case connected to a common word line WL1′, WL2′ and two are in each case connected to a common bit line pair BL1A′, BL1B′ and BL2A′, BL2B′. The memory cells have in each case a memory transistor T11s′, T112s′, T21s′, T22s′ and in each case a selection transistor T11a′, T12a′, T21a′, T22a′. The gate connections of the selection transistors T11a′–T22a′ of a row of the memory matrix are in each case connected to a common word line WL1′, WL2′, the drain connections of the selection transistors T11a′–T22a′ of a column of the memory matrix are in each case connected to a first bit line BL1A′, BL2A′ of the bit line pair and the source connections of the memory transistors T11s′–T22s′ of a column of the memory matrix are in each case connected to a second bit line BL1B′, BL2B′ of the bit line pair. Moreover, the control electrodes of the memory transistors T11s′–T22s′ of a row of the memory matrix are in each case connected to a programming and read line PL1′, PL2′.
The programming and read-out operation for a cell of this memory matrix is explained below on the basis of the memory cell Z11′, the selection transistor of which is connected to the word line WL1′ and the memory transistor T11s′ of which and which are assigned the bit line pair BL1A′, BL1B′. The drain connection of the selection transistor T11a′ of this cell Z11′ is connected to the first bit line BL1A′ and the source connection of the memory transistor T11s′ is connected to the second bit line BL1B′. For programming the memory cell, a programming voltage is applied between the programming and read line PL1′ and the first bit line BL1A′. The word line WL1′ is likewise connected to the programming voltage. In order to prevent programming of the memory cell Z12′ connected to the same programming and read line PL1′, the first bit line BL2A′ of this column of the memory matrix is biased such that approximately half of the programming voltage present at the memory transistor T11s′ of the first memory cell Z11′ is then present at the memory transistor T12s′ of said cell. The further word line of the memory matrix WL2′ is connected to a potential at which the selection transistors connected to this word line turn off, in order to prevent programming of the memory cell Z21′ connected to the same bit line as the first memory cell Z11′.
In order to read out the memory state of a specific memory cell, for example the memory cell Z11′, suitable read potentials are applied to the word line WL1′ and the programming and read line PL1′ of said cell. Moreover, a voltage is applied between the first bit line BL1A′ and the second bit line BL1B′ by connecting the first bit line BL1A′ to a positive potential, for example, and the second bit line BL1B′, via a further read transistor T1′, to reference potential GND, for example. Not specifically illustrated in FIG. 2 is a detector circuit that identifies changes in the potential of the first bit line BL1A′. Such a change occurs depending on the memory state of the memory transistor T11s′, that is to say depending on whether the memory transistor T11s′ turns on or turns off when the read voltage is applied.
In the case of the memory cell explained previously, a control voltage corresponding to the programming voltage of the memory transistor is applied to the selection transistor Ta′ during the programming operation. The gate insulation layer 70′ of said selection transistor Ta′ must be suitably dimensioned for this in order to withstand this voltage which is very high in comparison with the customary drive voltage of the selection transistor. The dielectric strength of this selection transistor lies above the dielectric strength of the gate insulation layers of components which are fabricated for example in a BCD technology (BCD technology=bipolar-CMOS-DMOS technology). Although the fundamental structure of an EEPROM memory cell could also be realized in BCD technology, the problem exists in this case, however, that additional complicated method steps would be required in order to fabricate a high-voltage-proof gate insulation layer of the selection transistor that withstands the programming voltage.